Description
The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa..
Features
- Zero Bus Latency, no dead cycles between Write and Read cycles.
- Fast clock speed: 200, 166, 133, 100 MHz.
- Fast access time: 3.2, 3.6, 4.2, 5.0 ns.
- Internally synchronized registered outputs eliminate the need to control OE.
- Single 3.3V.
- 5% and +5% power supply VCC.
- Separate VCCQ for 3.3V or 2.5V I/O.
- Single WEN (Read/Write) control pin.
- Positive clock-edge triggered, address, data, and control signal registers for f.
