GVT7C1359A
Key Features
- Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable (OE) and the Match Output Enable (MOE)
- The data outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous
- Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins
- Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV)
- Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE, CE2, and CE2)
- The outputs of the data input registers are pared with data in the memory array and a match signal is generated
- The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK)
- Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle
- WRITE cycles can be one to two bytes wide as controlled by the write control inputs
- Individual byte write allows individual byte to be written
