GVT7C1359A Datasheet, Cypress Semiconductor

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* Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock sp.

Low-profile JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-e.

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Selection Guide.