S6J311D Datasheet | Cypress

Features This section explains the features of the S6J3110 series. Cortex-R5 Core This section explains the Cortex-R5 CPU core. - Arm® Cortex®-R5 - 32-bit Arm architecture  2-instruction issuance super scalar  8-stage pipeline - Arm v7/Thumb®-2 instruction set - MPU (memory protection) equipped  16-area support - ECC support for the TCM ports for RAM  1-bit error correction and 2-bit error detection (SEC-DED) - TCM ports  2 TCM ports - ATCM port - BTCM port (B0TCM, B1TCM) - Caches  Instruction cache 16 KB  Data cache 16 KB - VIC port  Low latency interrupt - AXI master interface  64-bit AXI interface (instruction/data access)  32-bit AXI interface (I/O access) - AXI slave interface  64-bit AXI interface (TCM port access) - ETM-R5 trace Peripheral Functions This section explains peripheral functions. - Clock generation  Main clock oscillation (4 MHz)  No sub clock oscillation  CR oscillation (100 k Hz)  CR oscillation (4 MHz) - Built-in flash memory size  Program: 4096 K + 64 KB (S6J311Eyz C- ) / 3072K + 64KB (S6J311Dy AC- )  Work: 112 KB (S6J311Eyz C- ) / 112 KB (S6J311Dy AC- ) - y: J/H, z: A/B - Built-in RAM size  TCRAM 64 KB  System SRAM 256 KB (S6J311Eyz C- ) / 192 KB (S6J311Dy AC- )  Backup RAM 64 KB (S6J311Eyz C- ) / 64 KB (S6J311Dy AC- ) - y: J/H, z: A/B - General-purpose ports: 150 channels (S6J311x JAC- )/116 channels (S6J311x Hz C- ) - x: E/D, z: A/B - DMA controller  Up to 16 channels can be activated simultaneously. - A/D converter (successive approximation type)  12-bit resolution, 2 units mounted: Max 64 channels (32 channels + 32 channels) - External interrupt input: 16 channels  Level ("H"/"L") and edge (rising/falling) can be detected. - Multi-function serial (transmission and reception FIFOs mounted): Max 22 channels <I2C>  Full-duplex double buffering system, 64-byte transmission FIFO, 64-byte reception FIFO.  Standard mode ( Max. 100kbps ) is supported only.  DMA transfer is supported (only for ch.0 to ch.7). <UART (asynchronous serial interface)>  Full...