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S71KL512SC0 Datasheet HyperFlash and HyperRAM Multi-Chip Package

Manufacturer: Cypress (now Infineon)

Download the S71KL512SC0 datasheet PDF. This datasheet also includes the S71KS512SC0 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (S71KS512SC0-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

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3 HyperBus MCP Family with HyperFlash and HyperRAM ............................................................

3 HyperBus MCP 3 V Signal Descriptions .........................

Overview

SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V Distinctive Characteristics ■ HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP) ❐ 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KS512SC0) ❐ 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KL512SC0) ❐ 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM (S71KL256SC0) ❐ FBGA 24-ball, 6  8  1.0 mm package ■ HyperBus Interface ❐ 1.8V I/O, 12 bus signals • Differential clock (CK/CK#) ❐ 3.0V I/O, 11 bus signals • Single ended clock (CK) ❐ Chip Select (CS#) ❐ 8-bit data bus (DQ[7:0]) ❐ Read-Write Data Strobe (RWDS) • Bidirectional Data Strobe/Mask • Output at the start of all transactions to indicate refresh latency • Output during read transactions as Read Data Strobe • Input during write transactions as Write Data Mask (HyperRAM only) ■ Optional Signals ❐ Reset ❐ INT# output to generate external interrupt • Busy to Ready Transition ❐ RSTO# Output to generate system level Power-On Reset (POR) • User configurable RSTO# Low period ■ High Performance ❐ Double-Data Rate (DDR) • Two data transfers per clock ❐ Up to 166-MHz clock rate (333 MB/s) at 1.8V VCC ❐ Up to 100-MHz clock rate (200 MB/s) at 3.0V VCC Cypress Semiconductor Corporation • 198 Champion Court Document Number: 002-03902 Rev.

Key Features

  • operation, and ordering options of the related memories have been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document modifies any information on the same topics established by the documents listed in Table 1 and should be used in conjunction with those documents. This document may also contain information that was not previously covered by the listed documents. The information is intended for hardware system designers and sof.

More Datasheets from Cypress (now Infineon)

Part Number Description
S71KL256SC0 HyperFlash and HyperRAM Multi-Chip Package
S71KS512SC0 HyperFlash and HyperRAM Multi-Chip Package