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Cypress Semiconductor Electronic Components Datasheet

W144 Datasheet

440BX AGPset Spread Spectrum Frequency Synthesizer

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PRELIMINARY
W144
440BX AGPset Spread Spectrum
Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
1 1 11
1 1 10
1 1 01
1 1 00
1 0 11
1 0 10
1 0 01
1 0 00
0 1 11
0 1 10
0 1 01
0 1 00
0 0 11
0 0 10
0 0 01
0 0 00
CPU_F, CPU1
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5 (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
Pin Configuration
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SDRAMIN
I2C
Logic
Stop
Clock
Control
PLL2
÷2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
Note:
1. Internal pull-up resistors should not be relied upon for setting
I/O pins HGH. Pin function with parentheses determined by
MODE pin resistor strapping. Unlike other I/O pins, input FS3
has an internal pull down resistor.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W144 Datasheet

440BX AGPset Spread Spectrum Frequency Synthesizer

No Preview Available !

PRELIMINARY
W144
Pin Definitions
Pin Name
CPU_F
Pin No.
44
CPU1
43
PCI2:5
PCI1/FS3
10, 11, 12,
13
8
PCI_F/MODE
7
CLK_STOP#
41
IOAPIC
48MHz/FS0
47
26
24MHz/FS1
25
REF1/FS2
46
REF0/
(PCI_STOP#)
2
SDRAMIN
15
SDRAM0:11
SDRAM_F
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
40
SCLK
SDATA
X1
24
23
4
X2
VDDQ3
VDDQ2
GND
5
1, 6, 14,
19, 27, 30,
36
42, 48
3, 9, 16,
22, 33, 39,
45
Pin
Type
O
O
O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I
O
O
I
I/O
I
I
P
P
G
Pin Description
Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to
VDDQ2. See Tables 2 and 6 for detailed frequency information.
CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control
pin. Output voltage swing is controlled by voltage applied to VDDQ2.
PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3.
Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input.
When an input, latches data selecting the frequency of the CPU and PCI outputs.
Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#
input. When an input, sets function of pin 2.
CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after
completing a full clock cycle (23 CPU clock latency). When brought HIGH, affected clock
outputs start, beginning with a full clock cycle (23 CPU clock latency).
IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing
is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output
can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will
be latched, which will set clock frequencies as described in Table 2.
24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output
can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be
latched, which will set clock frequencies as described in Table 2.
I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which
will set clock frequencies as described in Table 2. When an output, this pin provides a
fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.
Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F.
Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a
fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:11, SDRAM_F).
Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided
at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
CLK_STOP# input is set LOW.
Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN
input which is not affected by the CLK_STOP# input
Clock pin for I2C Circuitry
Data pin for I2C Circuitry
Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI
outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect
to 2.5V or 3.3V.
Ground Connections: Connect all ground pins to the common system ground plane.
2


Part Number W144
Description 440BX AGPset Spread Spectrum Frequency Synthesizer
Maker Cypress Semiconductor
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W144 Datasheet PDF






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