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Cypress Semiconductor Electronic Components Datasheet

W40S11-23 Datasheet

Clock Buffer/Driver

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W40S11-23
Features
• Thirteen skew-controlled CMOS clock outputs
(SDRAM0:12)
• Supports three SDRAM DIMMs
• Ideal for high-performance systems designed around
Intel’s latest chip set
• I2C serial configuration interface
• Clock Skew between any two outputs is less than 250 ps
• 1- to 5-ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 300-mil
SOIC (Small Outline Integrated Circuit)
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15,
which is ideal for driving SDRAM DIMMs.
Block Diagram
Clock Buffer/Driver
Key Specifications
Supply Voltages:........................................... VDD = 3.3V±5%
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................VDD + 0.5V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns
Output Edge Rate:.............................................. >1.5 V/ns
Output Clock Skew: .................................................. ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance: ...............................................15typical
Output Type: ................................................ CMOS rail-to-rail
Pin Configuration
SDATA
SCLOCK
Serial Port
Device Control
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SOIC
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 SDRAM11
26 SDRAM10
25 GND
24 VDD
23 SDRAM9
22 SDRAM8
21 GND
20 VDD
19 SDRAM7
18 SDRAM6
17 GND
16
15
GSCNLDOCK[1]
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 28, 1999 rev. **


Cypress Semiconductor Electronic Components Datasheet

W40S11-23 Datasheet

Clock Buffer/Driver

No Preview Available !

W40S11-23
Pin Definitions
Pin Name
Pin
No.
SDRAM0:12
BUF_IN
2, 3, 6, 7, 10,
11, 18, 19,
22, 23, 26,
27, 12
9
SDATA
14
SCLOCK
15
VDD
GND
1, 5, 13, 20,
24, 28
4, 8, 16, 17,
21, 25
Pin
Type
O
I
I/O
I
P
G
Pin Description
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to
within ± 250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
I2C Data input: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kpull-up resistor.
I2C clock input: The I2C data clock should be presented to this input as described in
the I2C section of this data sheet. Internal 250-kpull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to 3.3V
supply.
Ground Connection: Connect all ground pins to the common system ground plane.
Functional Description
Output Drivers
The W40S11-23 output buffers are CMOS type which deliver
a rail-to-rail (GND to VDD) output voltage swing into a nominal
Table 1. Byte Writing Sequence
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15.
Operation
Data is written to the W40S11-23 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Byte
Sequence
1
Byte Name
Slave Address
2 Command
Code
3 Byte Count
4 Data Byte 0
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
Bit Sequence
11010010
Dont Care
Dont Care
Refer to Table 2
Dont Care
Byte Description
Commands the W40S11-23 to accept the bits in Data Bytes 06 for in-
ternal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-23
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W40S11-23, therefore bit values are ignored (dont care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W40S11-23, therefore bit values are ignored (dont care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
The data bits in these bytes set internal W40S11-23 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 2, Data Byte Serial Configuration Map.
Refer to Cypress Frequency Timing Generators.
2


Part Number W40S11-23
Description Clock Buffer/Driver
Maker Cypress Semiconductor
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