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Dallas Semiconductor

DS1350W Datasheet Preview

DS1350W Datasheet

3.3V 4096K Nonvolatile SRAM

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DS1350W
PRELIMINARY
DS1350W
3.3V 4096K Nonvolatile SRAM
with Battery Monitor
FEATURES
10 years minimum data retention in the absence of
external power
Data is automatically protected during power loss
Power supply monitor resets processor when VCC
power loss occurs and holds processor in reset during
VCC ramp–up
Battery monitor checks remaining capacity daily
Read and write access times as fast as 150 ns
Unlimited write cycle endurance
Typical standby current 50 µA
Upgrade for 512K x 8 SRAM, EEPROM or Flash
Lithium battery is electrically disconnected to retain
freshness until power is applied for the first time
Optional industrial temperature range of –40°C to
+85°C, designated IND
New PowerCap Module (PCM) package
– Directly surface–mountable module
– Replaceable snap–on PowerCap provides lith-
ium backup battery
– Standardized pinout for all nonvolatile SRAM
products
– Detachment feature on PowerCap allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
BW
A15
A16
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 GND VBAT
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34–PIN POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0–A18
– Address Inputs
DQ0–DQ7 – Data In/Data Out
CE – Chip Enable
WE – Write Enable
OE – Output Enable
RST
– Reset Output
BW – Battery Warning Output
VCC
GND
– Power (+3.3 Volts)
– Ground
NC – No Connect
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DESCRIPTION
The DS1350W 3.3V 4096K Nonvolatile SRAM is a
4,194,304–bit, fully static, nonvolatile SRAM organized
as 524,288 words by eight bits. Each NV SRAM has a
self–contained lithium energy source and control cir-
cuitry which constantly monitors VCC for an out–of–tol-
erance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1350W has dedi-
cated circuitry for monitoring the status of VCC and the
status of the internal lithium battery. DS1350W devices
in the PowerCap Module package are directly surface
mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM mod-
ule. The devices can be used in place of 512K x 8
SRAM, EEPROM or Flash components.
022598 1/11




Dallas Semiconductor

DS1350W Datasheet Preview

DS1350W Datasheet

3.3V 4096K Nonvolatile SRAM

No Preview Available !

DS1350W
READ MODE
The DS1350W executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 19 address inputs (A0 - A18)
defines which of the 524,288 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within tACC (Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either tCO for CE or tOE
for OE rather than address access.
WRITE MODE
The DS1350W excutes a write cycle whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The later occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in tODW from its
falling edge.
DATA RETENTION MODE
The DS1350W provides full functional capability for VCC
greater than 3.0 volts and write protects by 2.8 volts.
Data is maintained in the absence of VCC without any
additional support circuitry. The nonvolatile static RAMs
constantly monitor VCC. Should the supply voltage
decay, the NV SRAMs automatically write protect them-
selves, all inputs become “don’t care,” and all outputs
become high impedance. As VCC falls below approxi-
mately 2.5 volts, the power switching circuit connects
the lithium energy source to RAM to retain data. During
power–up, when VCC rises above approximately
2.5 volts, the power switching circuit connects external
VCC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after VCC
exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1350W has the ability to monitor the external
VCC power supply. When an out–of–tolerance power
supply condition is detected, the NV SRAM warns a pro-
cessor–based system of impending power failure by
asserting RST. On power up, RST is held active for 200
ms nominal to prevent system operation during pow-
er–on transients and to allow tREC to elapse. RST has
an open–drain output driver.
BATTERY MONITORING
The DS1350W automatically performs periodic battery
voltage monitoring on a 24 hour time interval. Such
monitoring begins within tREC after VCC rises above VTP
and is suspended when power failure occurs.
After each 24 hour period has elapsed, the battery is
connected to an internal 1Mtest resistor for one
second. During this one second, if battery voltage falls
below the battery voltage trip point (2.6V), the battery
warning output BW is asserted. Once asserted, BW
remains active until the module is replaced. The battery
is still retested after each VCC power–up, however, even
if BW is active. If the battery voltage is found to be higher
than 2.6V during such testing, BW is de–asserted and
regular 24–hour testing resumes. BW has an open–
drain output driver.
FRESHNESS SEAL
Each DS1350W is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guarantee-
ing full energy capacity. When VCC is first applied at a
level greater than VTP, the lithium energy source is
enabled for battery backup operation.
PACKAGES
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base
along with contacts for connection to the lithium battery
in the DS9034PC PowerCap. The PowerCap Module
package design allows a DS1350W device to be sur-
face mounted without subjecting its lithium backup bat-
tery to destructive high–temperature reflow soldering.
After a DS1350W module base is reflow soldered, a
DS9034PC is snapped on top of the base to form a com-
plete Nonvolatile SRAM module. The DS9034PC is
keyed to prevent improper attachment. DS1350W mod-
ule bases and DS9034PC PowerCaps are ordered sep-
arately and shipped in separate containers. See the
DS9034PC data sheet for further information.
022598 2/11


Part Number DS1350W
Description 3.3V 4096K Nonvolatile SRAM
Maker Dallas Semiconductor
PDF Download

DS1350W Datasheet PDF





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