The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1350AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1350Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 2.7 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.7 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1350AB and 4.5 volts for the
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system
operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver.
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ=test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
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