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Dallas Semiconductor

DS1495 Datasheet Preview

DS1495 Datasheet

(DS1495 / DS1497) RAMified Real Time Clock

No Preview Available !

DS1495/DS1497
DS1495/DS1497
RAMified Real Time Clock
FEATURES
Ideal for EISA bus PCs
Functionally compatible with MC146818 in 32 KHz
mode
Totally nonvolatile with over 10 years of operation in
www.DataSheet4U.comthe absence of power
Self-contained subsystem includes lithium, quartz,
and support circuitry
Counts seconds, minutes, hours, day of the week,
date, month, and year with leap year compensation
Binary or BCD representations of time, calendar, and
alarm
12- or 24-hour clock with AM and PM in 12-hour mode
Daylight Savings Time option
Interfaced with software as 64 register/RAM locations
plus 8K x 8 of static RAM
– 14 bytes of clock and control registers
– 50 bytes of general and control registers
– Separate 8K x 8 nonvolatile SRAM
Programmable square wave output signal
Bus-compatible interrupt signals (IRQ)
Three interrupts are separately software-maskable
and testable:
– Time-of-day alarm once/second to once/day
– Periodic rates from 122 µs to 500 ms
– End-of-clock update cycle
28-pin JEDEC footprint
Available as chip (DS1495/DS1495S) or stand alone
module with embedded lithium battery and crystal
(DS1497)
ORDERING INFORMATION
DS1495
DS1495S
DS1497
RTC Chip; 28–pin DIP
RTC Chip; 28–pin SOIC
RTC Module; 28–pin DIP
PIN ASSIGNMENT
A0
A1
X2
X1
STBY
D0
D1
D2
D3
D4
D5
D6
D7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A2
27 A3
26 VDD
25 SQW
24 A4
23 A5
22 VBAT
21 IRQ
20 RESET
19 RD
18 BGND
17 WR
16 XRAM
15 RTC
DS1495S 28-Pin SOIC (330 mil)
A0
A1
X2
X1
STBY
D0
D1
D2
D3
D4
D5
D6
D7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A2
27 A3
26 VDD
25 SQW
24 A4
23 A5
22 VBAT
21 IRQ
20 RESET
19 RD
18 BGND
17 WR
16 XRAM
15 RTC
DS1495 28-Pin DIP (600 mil)
A0
A1
NC
NC
STBY
D0
D1
D2
D3
D4
D5
D6
D7
V SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A2
27 A3
26 VDD
25 SQW
24 A4
23 A5
22 NC
21 IRQ
20 RESET
19 RD
18 NC
17 WR
16 XRAM
15 RTC
DS1497 28-Pin Encapsulated Package (720 mil)
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
020894 1/19




Dallas Semiconductor

DS1495 Datasheet Preview

DS1495 Datasheet

(DS1495 / DS1497) RAMified Real Time Clock

No Preview Available !

DS1495/DS1497
PIN DESCRIPTIONS
VDD, VSS Bus operational power is supplied to the part
via these pins. The voltage level present on these pins
should be monitored to transition between operational
power and battery power.
D0-D7 – Data Bus (bidirectional): Data is written into
the device from the data bus if either XRAM or RTC is
asserted during a write cycle at the rising edge of a WR
pulse. Data is read from the device and driven onto the
data bus if either XRAM or RTC is asserted during a
read cycle when the RD signal is low.
A0-A5 – Address Bus (input): Various internal regis-
ters of the device are selected by these lines. When
www.DataSheet4U.coRmTC is asserted, A0 selects between the indirect ad-
dress register and RTC data register. When the XRAM
is asserted, A0-A5 addresses a 32–byte page of RAM.
When A5 is high, the RAM page register is accessible.
When A5 is low, A0-A4 address the 32-byte page of
RAM.
RD – Read Strobe (input): Data is read from the se-
lected register and driven onto the data bus by the de-
vice when this line is low and either RTC or XRAM is as-
serted.
WR – Write Strobe (input): Data is written into the de-
vice from the data bus on the rising edge after a low
pulse on this line when the device has been selected by
either the XRAM or RTC signals.
STBY – Standby (input): Accesses to the device are
inhibited and outputs are tri-stated to a high impedance
state when this signal is asserted low. All data in RAM of
the device is preserved. The real time clock continues
to keep time.
If a read or write cycle is in progress when the STBY sig-
nal is asserted low, the internal cycle will be terminated
when either the external cycle completes or when the in-
ternal chip enable condition (VDD is 4.25 volts, typical) is
negated, whichever occurs first.
RTC – Real Time Clock Select (input): When this sig-
nal is asserted low, the real time clock registers are ac-
cessible. Registers are selected by the A0 line. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
SQW – Square Wave (output): Frequency selectable
output. Frequency is selected by setting register A bits
RSO-RS3. See Table 2 for frequencies that can be se-
lected.
XRAM – Extended RAM Select (input): When this sig-
nal is asserted low, the extended RAM bytes are acces-
sible. The XRAM page register is selected when the A5
address line is high. A 32-byte page of RAM is accessi-
ble when A5 is low. A0-A4 select the bytes within the
page of RAM pointed to by the page register. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
IRQ – Interrupt Request (output): The IRQ signal is
an active low, open drain output that is used as a proces-
sor interrupt request. The IRQ output follows the state
of the IRQF bit (bit 7) in status register C. IRQ can be
asserted by the alarm, update ended, or periodic inter-
rupt functions depending on the configuration of
register B.
RESET – Reset (input): The reset signal is used to ini-
tialize certain registers to allow proper operation of the
RTC module. When RESET is low, the following oc-
curs.
1. The following register bits are cleared:
a. Periodic interrupt (PIE)
b. Alarm interrupt enable (AIE)
c. Update ended interrupt (UF)
d. Interrupt request flag (IRQF)
e. Periodic interrupt flag (PF)
f. Alarm interrupt flag (AF)
g. Square wave output enable (SQWE)
h. Update ended interrupt enable (UIE)
2. The IRQ pin is in the high impedance state.
3. The RTC is not processor accessible.
020894 2/19


Part Number DS1495
Description (DS1495 / DS1497) RAMified Real Time Clock
Maker Dallas Semiconductor
Total Page 19 Pages
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