DS1495/DS1497
PIN DESCRIPTIONS
VDD, VSS – Bus operational power is supplied to the part
via these pins. The voltage level present on these pins
should be monitored to transition between operational
power and battery power.
D0-D7 – Data Bus (bidirectional): Data is written into
the device from the data bus if either XRAM or RTC is
asserted during a write cycle at the rising edge of a WR
pulse. Data is read from the device and driven onto the
data bus if either XRAM or RTC is asserted during a
read cycle when the RD signal is low.
A0-A5 – Address Bus (input): Various internal regis-
ters of the device are selected by these lines. When
www.DataSheet4U.coRmTC is asserted, A0 selects between the indirect ad-
dress register and RTC data register. When the XRAM
is asserted, A0-A5 addresses a 32–byte page of RAM.
When A5 is high, the RAM page register is accessible.
When A5 is low, A0-A4 address the 32-byte page of
RAM.
RD – Read Strobe (input): Data is read from the se-
lected register and driven onto the data bus by the de-
vice when this line is low and either RTC or XRAM is as-
serted.
WR – Write Strobe (input): Data is written into the de-
vice from the data bus on the rising edge after a low
pulse on this line when the device has been selected by
either the XRAM or RTC signals.
STBY – Standby (input): Accesses to the device are
inhibited and outputs are tri-stated to a high impedance
state when this signal is asserted low. All data in RAM of
the device is preserved. The real time clock continues
to keep time.
If a read or write cycle is in progress when the STBY sig-
nal is asserted low, the internal cycle will be terminated
when either the external cycle completes or when the in-
ternal chip enable condition (VDD is 4.25 volts, typical) is
negated, whichever occurs first.
RTC – Real Time Clock Select (input): When this sig-
nal is asserted low, the real time clock registers are ac-
cessible. Registers are selected by the A0 line. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
SQW – Square Wave (output): Frequency selectable
output. Frequency is selected by setting register A bits
RSO-RS3. See Table 2 for frequencies that can be se-
lected.
XRAM – Extended RAM Select (input): When this sig-
nal is asserted low, the extended RAM bytes are acces-
sible. The XRAM page register is selected when the A5
address line is high. A 32-byte page of RAM is accessi-
ble when A5 is low. A0-A4 select the bytes within the
page of RAM pointed to by the page register. Data is
driven onto the data bus when RD is low. Data is re-
ceived from the bus when WR is pulsed low and then
high.
IRQ – Interrupt Request (output): The IRQ signal is
an active low, open drain output that is used as a proces-
sor interrupt request. The IRQ output follows the state
of the IRQF bit (bit 7) in status register C. IRQ can be
asserted by the alarm, update ended, or periodic inter-
rupt functions depending on the configuration of
register B.
RESET – Reset (input): The reset signal is used to ini-
tialize certain registers to allow proper operation of the
RTC module. When RESET is low, the following oc-
curs.
1. The following register bits are cleared:
a. Periodic interrupt (PIE)
b. Alarm interrupt enable (AIE)
c. Update ended interrupt (UF)
d. Interrupt request flag (IRQF)
e. Periodic interrupt flag (PF)
f. Alarm interrupt flag (AF)
g. Square wave output enable (SQWE)
h. Update ended interrupt enable (UIE)
2. The IRQ pin is in the high impedance state.
3. The RTC is not processor accessible.
020894 2/19
