Datasheet4U Logo Datasheet4U.com

DS3101 - Stratum 3/3E Timing Card IC

General Description

When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements.

Key Features

  • Synchronization Subsystem for Stratum 3E, 3, 4E, and 4, SMC and SEC - Meets Requirements of GR-1244 Stratum 3/3E, GR-253, G.812 Types I, III, and IV, and G.813 - Stratum 3E Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.5mHz to 70Hz - Hitless Reference Switching on Loss of Input - Phase Build-Out and Transient Absorption - Locks To and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261 14 Input Clocks - 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and An.

📥 Download Datasheet

Datasheet Details

Part number DS3101
Manufacturer Dallas Semiconductor
File Size 1.18 MB
Description Stratum 3/3E Timing Card IC
Datasheet download datasheet DS3101 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DS3100 Stratum 3/3E Timing Card-IC Maxim Integrated Products
DS3100 Stratum 2/3E/3 Timing Card-IC Microsemi
DS3104-SE Line Card Timing IC Maxim Integrated Products
DS3105 Line Card Timing IC Maxim Integrated Products
DS310W Surface Mount Schottky Barrier Rectifier SEMIPOWER

Other Datasheets by Dallas Semiconductor

Part Number Description
DS3802 Advanced NV SRAM Battery
DS3803 1024k Flexible NV SRAM SIMM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com DS3101 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL complies with the Stratum 3 and 3E requirements of GR-1244, GR-253, and the requirements of G.812 Type III and G.813.