DS3803 Datasheet | Dallas Semiconductor

FEATURES Flexibly organized as 32k x 32, 64k x 16 or 128k x 8bits 10 years minimum data retention in the absence of external power Nonvolatile circuitry transparent to and independent from host system Automatic write protection circuitry safeguards against data loss Separate control and data signals for each SRAM allow byte, word or doubleword access Fast access time of 70 ns Full VCC ± 10% operating range Employs popular JEDEC standard 72-position SIMM connector Extremely thin design built using TSOPpackage IC ponents PIN ASSIGNMENT 256K SRAM 256K SRAM 256K SRAM 256K SRAM DS3803 72-Pin SIMM PIN DESCRIPTION A0 - A14 D0A - D7A D0B - D7B D0C - D7C D0D - D7D CEA - CED WEA - WED OEA - OED VCC GND NC Address Inputs Data Inputs/Outputs, Byte A Data Inputs/Outputs, Byte B Data Inputs/Outputs, Byte C Data Inputs/Outputs, Byte D Chip Enable Inputs Write Enable Inputs Output Enable Inputs +5V Power Supply Ground No Connect DESCRIPTION The DS3803 is a self-contained, 1,048,576-bit, nonvolatile static RAM which can be flexibly organized as 32k x 32, 64k x 16 or 128k x 8. Built using four 32k x 8 SRAMs, four nonvolatile control ICs and four lithium batteries, this nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS3803 employs the popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry. 1 of 10 112299 .. READ MODE The DS3803 executes a read cycle whenever WE (Write enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 A14) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available to the data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If CE and OE access...