DS3101 Datasheet | Dallas Semiconductor

DESCRIPTION When paired with an external TCXO or OCXO, the DS3101 is a highly integrated central timing and synchronization solution for SONET/SDH network elements. With 14 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. All input clocks are continuously monitored for frequency accuracy and activity. Any two of the input clocks can be selected as the references for the two core DPLLs. The T0 DPLL plies with the Stratum 3 and 3E requirements of GR-1244, GR-253, and the requirements of G.812 Type III and G.813. From the output of the core DPLLs, a wide variety of output clock frequencies and frame pulses can be produced simultaneously on the 11 output clock pins. Two DS3101 devices can be configured in a master/slave arrangement for timing card equipment protection. The DS3101 registers and I/O pins are backward patible with Semtech’s ACS8520 and ACS8530 timing card ICs. The DS3101 is functionally equivalent to a DS3100 without integrated BITS transceivers. FEATURES Synchronization Subsystem for Stratum 3E, 3, 4E, and 4, SMC and SEC - Meets Requirements of GR-1244 Stratum 3/3E, GR-253, G.812 Types I, III, and IV, and G.813 - Stratum 3E Holdover Accuracy with Suitable External Oscillator - Programmable Bandwidth, 0.5m Hz to 70Hz - Hitless Reference Switching on Loss of Input - Phase Build-Out and Transient Absorption - Locks To and Generates 125MHz for Gigabit Synchronous Ethernet per ITU-T G.8261 14 Input Clocks - 10 CMOS/TTL Inputs Accept 2k Hz, 4k Hz, and Any Multiple of 8k Hz Up to 125MHz - Two LVDS/LVPECL/CMOS/TTL Inputs Accept Nx8k Hz Up to 125MHz Plus 155.52MHz - Two 64k Hz posite Clock Receivers - Continuous Input Clock Quality Monitoring - Separate 2/4/8k Hz Frame Sync Input 11 Output Clocks - Five CMOS/TTL Outputs Drive Any Internally Produced Clock Up to 77.76MHz - Two LVDS Outputs Each Drive Any Internally Produced Clock Up to 311.04MHz - One 64k Hz posite...