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Data Delay Devices

3D7424 Datasheet Preview

3D7424 Datasheet

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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MONOLITHIC QUAD 4-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7424)
3D7424
FEATURES
Four indep’t programmable lines on a single chip
All-silicon CMOS technology
Low quiescent current (5mA typical)
Leading- and trailing-edge accuracy
Vapor phase, IR and wave solderable
Increment range: 0.75ns through 400ns
Delay tolerance: 3% or 2ns (see Table 1)
Line-to-line matching: 1% or 1ns typical
Temperature stability: ±1.5% typical (-40C to 85C)
Vdd stability: ±0.5% typical (4.75V to 5.25V)
Minimum input pulse width: 10% of total delay
PACKAGES
I1
SC
I2
I3
I4
SI
GND
1 14
2 13
3 12
4 11
5 10
69
78
DIP-14
3D7424-xx
VDD
AL
O1
SO
O2
O3
O4
I1
SC
I2
I3
I4
SI
GND
1 14 VDD
2 13 AL
3 12 O1
4 11 SO
5 10 O2
6 9 O3
7 8 O4
SOIC-14
3D7424D-xx
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7424 device is a small, versatile, quad 4-bit programmable
I1-I4 Signal Inputs
monolithic delay line. Delay values, programmed via the serial interface,
O1-O4 Signal Outputs
can be independently varied over 15 equal steps. The step size (in ns) is
AL Address Latch In
determined by the device dash number. Each input is reproduced at the
SC Serial Clock In
corresponding output without inversion, shifted in time as per user
SI Serial Data In
selection. For each line, the delay time is given by:
SO Serial Data Out
TDn = T0 + An * TI
where T0 is the inherent delay, An is the delay address of the n-th line
and TI is the delay increment (dash number). The desired addresses are
VDD 5.0V
GND Ground
shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The
serial interface can also be used to enable/disable each delay line. The 3D7424 operates at 5 volts and
has a typical T0 of 6ns. The 3D7424 is TTL/CMOS-compatible, capable of sourcing or sinking 4mA loads,
and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-
insertable DIP and a space saving surface mount 14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
Part
Number
3D7424-.75
3D7424-1
3D7424-1.5
3D7424-2
3D7424-4
3D7424-5
3D7424-10
3D7424-15
3D7424-20
3D7424-40
3D7424-50
3D7424-100
3D7424-200
3D7424-400
DELAYS & TOLERANCES (NS)
Delay Inherent Total
Relative
Step
Delay
Delay
Tolerance
.75 ± 0.19
1.0 ± 0.25
1.5 ± 0.38
6.0 ± 2.0 17.25 ± 2.0 3% or 0.50ns
6.0 ± 2.0 21.0 ± 2.0 3% or 0.50ns
6.0 ± 2.0 28.5 ± 2.0 3% or 0.50ns
2.0 ± 0.50
4.0 ± 1.00
5.0 ± 1.25
6.0 ± 2.0
6.0 ± 2.0
6.0 ± 2.0
36.0 ± 2.0 3% or 0.75ns
66.0 ± 2.0 3% or 0.75ns
81.0 ± 2.5 3% or 0.75ns
10 ± 2.50
15 ± 3.75
20 ± 5.00
6.0 ± 2.0
6.0 ± 2.0
6.0 ± 2.0
156 ± 5.0 3% or 1.25ns
231 ± 7.5 3% or 1.88ns
306 ± 10 3% or 2.50ns
40 ± 10.0
50 ± 10.0
100 ± 12.5
6.0 ± 2.0
6.0 ± 2.0
6.0 ± 2.0
606 ± 20 3% or 5.00ns
756 ± 25 3% or 6.25ns
1506 ± 50 3% or 12.5ns
200 ± 20.0 6.0 ± 2.0 3006 ± 100 3% or 25.0ns
400 ± 40.0 6.0 ± 2.0 6006 ± 200 3% or 50.0ns
INPUT RESTRICTIONS
Max Frequency
Min Pulse Width
Recom’d Absolute Recom’d Absolute
19 MHz 166 MHz 26 ns
3.0 ns
16 MHz 166 MHz 32 ns
3.0 ns
12 MHz 111 MHz 43 ns
4.5 ns
9.2 MHz 83 MHz
54 ns
6.0 ns
5.0 MHz 83 MHz
99 ns
6.0 ns
4.1 MHz 66 MHz 122 ns
7.5 ns
2.1 MHz 33 MHz 234 ns
15.0 ns
1.4 MHz 22 MHz 347 ns
22.5 ns
1.0 MHz 16 MHz 459 ns
30.0 ns
550 KHz 8.3 MHz 909 ns
60.0 ns
440 KHz 6.6 MHz 1.2 us
75.0 ns
220 KHz 3.3 MHz 2.3 us
150 ns
110 KHz 1.6 MHz 4.5 us
300 ns
55 KHz 833 KHz 9.0 us
600 ns
NOTE: Any increment between 0.75ns and 400ns not shown is also available as standard
See page 4 for details regarding input restrictions
2006 Data Delay Devices
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1




Data Delay Devices

3D7424 Datasheet Preview

3D7424 Datasheet

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

No Preview Available !

3D7424
APPLICATION NOTES
THEORY OF OPERATION
The quad 4-bit programmable 3D7424 device
architecture is comprised of four independently
operating delay lines. Each delay line produces
at its output a replica of the signal present at its
input, shifted in time. A single delay line is
comprised of a number of delay cells connected
in series. Delay selection is achieved by routing
one output in each string of cells to its respective
output pin (O1-O4). The delay of each of the four
lines can be controlled independently, via the
serial interface, as described in the next section.
The change in delay from one address setting to
the next is called the increment, or LSB. It is
nominally equal to the device dash number. The
minimum delay, achieved by setting the address
of a line to zero, is called the inherent delay.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
I4
DELAY
LINE
I3
DELAY
LINE
I2
DELAY
LINE
I1
DELAY
LINE
ADDR4
ADDR3
ADDR2
ADDR1 ENABLES
AL 20-BIT LATCH
SI
SC 20-BIT SHIFT REGISTER
Figure 1: Functional block diagram
O4
O3
O2
O1
SO
PROGRAMMED DELAY INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D7424 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in Table 2,
and the associated timing diagram is shown in
Figure 2. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
impedance state, while setting it high returns the
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
TABLE 2: BIT SEQUENCE
Bit Delay
Line
14
23
32
41
51
6
7
8
92
10
11
12
13 3
14
15
16
17 4
18
19
20
Function
Output Enable
Output Enable
Output Enable
Output Enable
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
LATCH
(AL)
tCW tCW
CLOCK
(SC)
SERIAL
INPUT
(SI)
tDSC
NEW
BIT 1
SERIAL
OUTPUT
(SO)
OLD
BIT 1
tDHC
NEW
BIT 2
tPCQ
OLD
BIT 2
DELAY
TIMES
PREVIOUS VALUES
tLW
tCSL
NEW
BIT 20
OLD
BIT 20
tLDX
NEW
BIT 1
tLDV
NEW
VALUES
Figure 2: Serial interface timing diagram
Doc #06019
6/5/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2


Part Number 3D7424
Description MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE
Maker Data Delay Devices
Total Page 6 Pages
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