DFP2INT
Description
Global system clock Global system reset Enable computing Data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved.
Key Features
- Full IEEE-754 compliance Single precision real input numbers Double word output numbers(4 Bytes) Simple interface No programming required 2 levels pipelining Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support
