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DRPIC1655X Datasheet Preview

DRPIC1655X Datasheet

High Performance Configurable 8-bit RISC Microcontroller

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DRPIC1655X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.15
OVERVIEW
The DRPIC1655X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core,
dedicated for operation with fast (typically on-
chip) dual ported memory. The core has been
designed with a special concern about low
power consumption.
DRPIC1655X soft core is software-
compatible with the industry standard
PIC16C554 and PIC16C558. It implements an
enhanced Harvard architecture (i.e.
separate instruction and data memories) with
independent address and data buses. The 14
bit program memory and 8-bit dual port data
memory allow instruction fetch and data
operations to occur simultaneously. The
advantage of this architecture is that
instruction fetch and memory transfers can be
overlapped by multi stage pipeline, so that the
next instruction can be fetched from program
memory while the current instruction is
executed with data from the data memory.
The DRPIC1655X architecture is 4 times
faster compared to standard architecture. So
most instructions are executed within 1
system clock period, except the instructions
which directly operates on program counter
PC (GOTO, CALL, RETURN), this situation
require the pipeline to be cleared and
subsequently refilled. This operation takes
additional one clock cycle.
The DRPIC1655X Microcontroller fits
perfectly in applications ranging from high-
All trademarks mentioned in this document
are trademarks of their respective owners.
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode make this IP perfect
for applications where power consumption is
critical.
DRPIC1655X is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at
each stage of SoC design flow
CPU FEATURES
Software compatible with industry standard
PIC16C55X
Pipelined Harvard architecture 4 times
faster compared to original implementation
35 instructions
14 bit wide instruction word
Up to 32 K bytes of internal Data Memory
Up to 64K bytes of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesizable, static synchronous
design with no internal tri-states
Technology independent HDL Source
Code
1.4 GHz virtual clock frequency in a 0.18u
technological process
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




Digital Core Design

DRPIC1655X Datasheet Preview

DRPIC1655X Datasheet

High Performance Configurable 8-bit RISC Microcontroller

No Preview Available !

w w w . D a t a S h e ePt 4 UE. c oRm I P H E R A L S
Four 8 bit I/O ports
Four 8-bit corresponding TRIS registers
Interrupt feature on PORTB(7:4) change
Timer 0
8-bit timer/counter
Readable and Writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt generation on timer overflow
Edge select for external clock
Watchdog Timer
Configurable Time out period
7-bit software programmable prescaler
Dedicated independent Watchdog Clock input
Extended Interrupt Controller
Three individually maskable Interrupt sources
External interrupt INT
Timer Overflow interrupt
Port B[7:4] change interrupt
DoCD™ debug unit
Processor execution control
Run
Halt
Step into instruction
Skip instruction
Read-write all processor contents
Program Counter (PC)
Program Memory
Data Memory
Special Function Registers (SFRs)
Hardware Stack and Stack Pointer
Hardware execution breakpoints
Program Memory
Data Memory
Special Function Registers (SFRs)
Hardware breakpoints activated at a certain
Program address (PC)
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
Three wire communication interface
DELIVERABLES
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench
environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
CONFIGURATION
The following parameters of the DRPIC1655X
core can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
Number
levels
of
hardware
stack
Memories type
SLEEP mode
WATCHDOG Timer
Timer system
Interrupt system
PORTS A,B,C,D
DoCDTM Debug Unit
- 1-16
- default 8
- synchronous
- asynchronous
- used
- unused
- used / width
- unused
- used
- unused
- used
- unused
- used
- unused
- used
- unused
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.


Part Number DRPIC1655X
Description High Performance Configurable 8-bit RISC Microcontroller
Maker Digital Core Design
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