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74AUP1G04 - SINGLE INVERTER GATE

General Description

The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The 74AUP1G04 is a single inverter gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4 mA Output Drive at 3.0V.
  • Low Static Power Consumption ICC < 0.9µA.
  • Low Dynamic Power Consumption CPD = 6.1pF (Typical at 3.6V).
  • Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection Exce.

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Other Datasheets by Diodes Incorporated

Part Number Description
74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G02 SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G06 SINGLE INVERTER
74AUP1G07 SINGLE BUFFER/DRIVER
74AUP1G08 SINGLE 2 INPUT POSITIVE AND GATE

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Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G04 is a single inverter gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y=A Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • ±4 mA Output Drive at 3.0V • Low Static Power Consumption ICC < 0.9µA • Low Dynamic Power Consumption CPD = 6.1pF (Typical at 3.