74AUP1G00 - SINGLE 2 INPUT POSITIVE NAND GATE

Diodes

Datasheet Details

Part number	74AUP1G00
Manufacturer	DIODES ↗
File Size	329.36 KB
Description	SINGLE 2 INPUT POSITIVE NAND GATE
Datasheet	74AUP1G00-Diodes.pdf

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

Advanced Ultra Low Power (AUP) CMOS.
Supply Voltage Range from 0.8V to 3.6V.
±4 mA Output Drive at 3.0V.
Low Static Power Consumption ICC < 0.9µA.
Low Dynamic Power Consumption CPD = 6pF (Typical at 3.6V).
Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250mV at VCC = 3.0V.
IOFF Supports Partial-Power-Down Mode Operation.
ESD Protection Exceed.

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Published: Jul 25, 2015 |