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74AUP1G08 - SINGLE 2 INPUT POSITIVE AND GATE

Description

The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The 74AUP1G08 is a single, two-input, positive AND gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V.

Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4mA Output Drive at 3.0V.
  • Low Static Power Consumption Icc < 0.9µA.
  • Low Dynamic Power Consumption CPD = 6.3 pF (Typical at 3.6V).
  • Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The hysteresis is typically 250mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection Excee.

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Datasheet Details

Part number 74AUP1G08
Manufacturer Diodes Incorporated
File Size 343.44 KB
Description SINGLE 2 INPUT POSITIVE AND GATE
Datasheet download datasheet 74AUP1G08 Datasheet
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Full PDF Text Transcription

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74AUP1G08 SINGLE 2 INPUT POSITIVE AND GATE Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G08 is a single, two-input, positive AND gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Pin Assignments Y = A • B or Y = A + B Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • ±4mA Output Drive at 3.0V • Low Static Power Consumption Icc < 0.
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