74AUP1G09 Overview
The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The AUP1G09 is a single AND gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF.
74AUP1G09 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- 4mA Output Drive at 3.0V
- Low Static Power Consumption
- Low Dynamic Power Consumption
- Schmitt Trigger Action at all inputs makes the circuit tolerant
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- Latch-Up Exceeds 100mA per JESD 78, Class I
- Leadless Packages Named per JESD30E
