Datasheet4U Logo Datasheet4U.com

74AUP1G09 - SINGLE 2 INPUT POSITIVE AND GATE

General Description

The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The AUP1G09 is a single AND gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • 4mA Output Drive at 3.0V.
  • Low Static Power Consumption ICC < 0.9µA.
  • Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V).
  • Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250 mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection Exceed.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74AUP1G09 Low-power 2-input AND Gate NXP
74AUP1G09 Low-power 2-input AND gate nexperia
74AUP1G09-Q100 Low-power 2-input AND gate nexperia
74AUP1G00 Low-power 2-input NAND gate NXP Semiconductors
74AUP1G00 Low-power 2-input NAND gate nexperia

Other Datasheets by Diodes Incorporated

Part Number Description
74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G02 SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G04 SINGLE INVERTER GATE
74AUP1G06 SINGLE INVERTER
74AUP1G07 SINGLE BUFFER/DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AUP1G09 SINGLE 2 INPUT POSITIVE AND GATE WITH OPEN DRAIN OUTPUT Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The AUP1G09 is a single AND gate with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Pin Assignments Y = A • B or Y = A + B Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • 4mA Output Drive at 3.0V • Low Static Power Consumption ICC < 0.