| Part Number | 74AUP1G09 Datasheet |
|---|---|
| Manufacturer | Diodes Incorporated |
| Overview |
The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.
The AUP1G09 is a single AND gate with an open drain output designed .
* Advanced Ultra Low Power (AUP) CMOS * Supply Voltage Range from 0.8V to 3.6V * 4mA Output Drive at 3.0V * Low Static Power Consumption ICC < 0.9µA * Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V) * Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise an. |
74AUP1G09 Datasheet and Specifications PDF
The 74AUP1G09 is a SINGLE 2 INPUT POSITIVE AND GATE.
| Part Number | 74AUP1G09 Datasheet |
|---|---|
| Description | Low-power 2-input AND gate |
| Manufacturer | Nexperia |
| Overview |
The 74AUP1G09 is a single 2-input AND gate with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low sta.
and benefits
* Wide supply voltage range from 0.8 V to 3.6 V * CMOS low power dissipation * High noise immunity * Overvoltage tolerant inputs to 3.6 V * Low static power consumption; ICC = 0.9 μA (maximum) * Latch-up performance exceeds 100 mA per JESD 78 Class II Level B * Low noise overshoot and u. |
| Part Number | 74AUP1G09 Datasheet |
|---|---|
| Description | Low-power 2-input AND Gate |
| Manufacturer | NXP Semiconductors |
| Overview | The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-O. I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E exceeds 5000 V N MM J. |