74AUP1G09 - Low-power 2-input AND Gate

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NXP

74AUP1G09 Low-power 2-input AND Gate by NXP - Datasheet Preview — Datasheet preview – 74AUP1G09

Datasheet Details

Part number	74AUP1G09
Manufacturer	NXP
File Size	124.69 KB
Description	Low-power 2-input AND Gate
Datasheet	74AUP1G09 Datasheet
Additional preview pages of the 74AUP1G09 datasheet.

Product details

Description

The 74AUP1G09 provides the single 2-input AND gate with an open-drain output.

The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Features

I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages.

📁 Similar Datasheet

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Other Datasheets by NXP

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74AUP1G14 - Low-power Schmitt-trigger inverter
74AUP1G17 - Low-power Schmitt-trigger buffer

Published: Aug 31, 2009 |