74AUP1G00 Datasheet | Nexperia

description The 74AUP1G00 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits - Wide supply voltage range from 0.8 V to 3.6 V - CMOS low power dissipation - High noise immunity - plies with JEDEC standards: - JESD8-12 (0.8 V to 1.3 V) - JESD8-11 (0.9 V to 1.65 V) - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8C (2.7 V to 3.6 V) - ESD protection: - HBM JESD22-A114F Class 3A exceeds 5000 V - MM JESD22-A115-A exceeds 200 V - CDM JESD22-C101E exceeds 1000 V - Low static power consumption; ICC = 0.9 μA (maximum) - Latch-up performance exceeds 100 m A per JESD 78 Class II - Overvoltage tolerant inputs to 3.6 V - Low noise overshoot and undershoot < 10 % of VCC - IOFF circuitry provides partial Power-down mode operation - Multiple package options - Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia Low-power 2-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP1G00GW -40 °C to +125 °C Name TSSOP5 74AUP1G00GM -40 °C to +125 °C XSON6 74AUP1G00GN -40 °C to +125 °C XSON6 74AUP1G00GS -40 °C to +125 °C XSON6 74AUP1G00GX -40 °C to +125 °C X2SON5 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm plastic thermal enhanced extremely thin small outline package; no...