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74AUP2G02 - DUAL NOR GATE

General Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The 74AUP2G02 is a dual two-input NOR gate.

Both gates have push-pull outputs designed for operation over a power supply range of 0.8 V to 3.6 V.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4mA Output Drive at 3.0V.
  • Low Static Power Consumption ICC < 0.9µA.
  • Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V).
  • Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 25.

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NEW PRODUCT 74AUP2G02 DUAL NOR GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G02 is a dual two-input NOR gate. Both gates have push-pull outputs designed for operation over a power supply range of 0.8 V to 3.6 V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Each gate performs the positive Boolean function: Y = A + B or Y = A • B (Top View) X2-DFN1210-8 Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • ±4mA Output Drive at 3.0V • Low Static Power Consumption ICC < 0.