74AUP2G00
Overview
Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G00 is a dual two input NAND gate.
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- ±4mA Output Drive at 3.0V
- Low Static Power Consumption ICC < 0.9µA
- Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V)
- Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250 mV at VCC = 3.0V
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101)
- Latch-Up Exceeds 100mA per JESD 78, Class I
- Leadless Packages Named per JESD30E
