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74AUP2G00 Datasheet

The 74AUP2G00 is a Low-power dual 2-input NAND gate. Download the datasheet PDF and view key features and specifications below.

Part Number74AUP2G00
ManufacturerNXP Semiconductors
Overview The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. . and benefits  Wide supply voltage range from 0.8 V to 3.6 V  High noise immunity  Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
* JESD8-7 (1.2 V to 1.95 V)
* JESD8-5 (1.8 V to 2.7 V)
* JESD8-B (2.7 V to 3.6 V)  ESD protection:
* HBM JESD22-A114F Class 3A.
Part Number74AUP2G00
DescriptionDUAL NAND GATE
ManufacturerDiodes Incorporated
Overview Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G00 is a dual two input NAND gate. Both g.
* Advanced Ultra Low Power (AUP) CMOS
* Supply Voltage Range from 0.8V to 3.6V
* ±4mA Output Drive at 3.0V
* Low Static Power Consumption ICC < 0.9µA
* Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V)
* Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise a.
Part Number74AUP2G00
DescriptionLow-power dual 2-input NAND gate
ManufacturerNexperia
Overview The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. . and benefits
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
* JESD8-7 (1.2 V to 1.95 V)
* JESD8-5 (1.8 V to 2.7 V)
* JESD8-B (2.7 V to 3.6 V)
* ESD protection:
* HBM JESD22-A114F Class 3A.

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