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PI6CG33402 - 3.3V Very-Low Power 4-Output PCIe Clock Generator

General Description

The PI6CG33402 is a four-output very-low power PCIe Gen1/Gen2/ Gen3/ Gen4/ Gen5 clock generator.

It uses 25MHz crystal or CMOS reference as an input to generate the 100MHz low-power differential HCSL outputs with on-chip terminations.

Key Features

  • ÎÎ3.3V Supply Voltage ÎÎCrystal/CMOS Input: 25MHz ÎÎTwo Differential Low-Power HCSL Outputs with On-chip Termination ÎÎDefault ZOUT = 85Ω ÎÎIndividual Output Enable ÎÎReference CMOS Output ÎÎProgrammable Slew Rate and Output Amplitude for each Output ÎÎDifferential Outputs Blocked until PLL is Locked ÎÎSelectable 0%, -0.25%, or -0.5% Spread on Differential Outputs ÎÎStrapping pins or SMBus for Configuration ÎÎ3.3V Tolerant SMBus Interface Support ÎÎVery-Low Jitter Outputs àà Differential Cycle-t.

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Other Datasheets by Diodes Incorporated

Part Number Description
PI6CG33402C 3.3V Very-Low Power 4-Output PCIe Clock Generator
PI6CG33401C 3.3V Very-Low-Power 4-Output PCIe Clock Generator
PI6CG334Q 4-Output PCIe Gen 6 Clock Generator
PI6CG33201C 3.3V Very Low Power 2-Output PCIe Clock Generator
PI6CG33202C 3.3V Very Low Power 2-Output PCIe Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Pb Lead-free Green A product Line of Diodes Incorporated PI6CG33402 3.3V Very-Low Power 4-Output PCIe Clock Generator With On-chip Termination Features ÎÎ3.3V Supply Voltage ÎÎCrystal/CMOS Input: 25MHz ÎÎTwo Differential Low-Power HCSL Outputs with On-chip Termination ÎÎDefault ZOUT = 85Ω ÎÎIndividual Output Enable ÎÎReference CMOS Output ÎÎProgrammable Slew Rate and Output Amplitude for each Output ÎÎDifferential Outputs Blocked until PLL is Locked ÎÎSelectable 0%, -0.25%, or -0.5% Spread on Differential Outputs ÎÎStrapping pins or SMBus for Configuration ÎÎ3.3V Tolerant SMBus Interface Support ÎÎVery-Low Jitter Outputs àà Differential Cycle-to-Cycle Jitter <50ps àà Differential Output-to-Output Skew <50ps àà PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Compliant àà CMOS REFOUT Phase Jitter is < 0.