M13S128324A sdram equivalent, double data rate sdram.
* Double-data-rate architecture, two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CLK and CLK )
* DLL al.
Pin Name
Function
Pin Name
Function
A0~A11, BA0,BA1
Address inputs - Row address A0~A11 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks)
DM0~DM3
DM is an input mask signal for write data. DM0 corresponds to the .
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