M14F5121632A sdram equivalent, ddr ii sdram.
* JEDEC Standard
* VDD / VDDQ = 1.55V ± 0.075V
* Internal pipelined double-data-rate architecture; two data access per clock cycle
* Bi-directional differ.
Pin Name
A0~A12, BA0,BA1
DQ0~DQ15 RAS CAS WE VSS VDD
DQS, DQS (LDQS, LDQS UDQS, UDQS)
ODT
NC
Function
Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Command inpu.
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TAGS
Manufacturer
Related datasheet
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