FUNCTIONAL DESCRIPTION — The ’93 is a 4-bit ripple type binary counter. It consists of four master/slave
flip-flops which are internally connected to provide a divide-by-two section and a divide-by-eight section. Each
section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock
transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals aresubject to decoding spikes and should not beused forelocks or strobes.
The Qo output of each device is designed and specified to drive the rated fan-out plus the CPi input of the
device. A gated AND asynchronous Master Reset (MRi, MR2) is provided which overrides the clocks and resets
(clears) all the flip-flops. Since the output from the divide-by-two section is not internally connected to the
succeeding stages, the devices may be operated in various counting modes.
A. 4-Bit Ripple Counter— The output Qo must be externally connected to input CP1. The input count pulses
are applied to input CPo. Simultaneous divisions Of 2,4,8, and 16 are performed at the Qo, Q1, Q2, and Q3
outputs as shown in the Truth Table.
B. 3-Bit Ripple Counter — The input cou nt pulses are applied to input CP1. Simultaneous frequency divisions
of 2, 4, and 8 are available at the Q1, Q2, and Q3 outputs. Independent use of the first flip-flop is available
if the reset function coincides with reset of the 3-bit ripple-through counter.
H = HIGH Voltage Level
L = LOW Voltage Level
Qo Q1 Q2 03
1 HL L L
2 L HL L
3 HHL L
4 L L HL
5 HL HL
6 L HHL
9 HL L H
10 L H L H
11 H H L H
12 L L H H
13 H L H H
14 L H H H
15 H H H H
NOTE: Output Qo connected to CP1 .