N2SV12816FS-75B Datasheet | Elixir

.. N2SV12816FS-6K/75B N2SV6H16FS-6K/75B 64Mb/128Mb Synchronous DRAM Features - - - - - - - Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8, Full page Programmable Wrap: Sequential or Interleave Burst Read with Single Write Operation Automatic and Controlled Precharge mand - - - - - - Dual Data Mask for byte control (x16) Auto Refresh and Self Refresh 64ms refresh period (4K cycle) JEDEC standard 3.3V Power Supply LVTTL patible Package: 54-pin TSOP (II) Description The N2SV6H16FS is four-bank Synchronous DRAMs organized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS organized as 2 Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by binations of these signals and a mand decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (BS0, BS1) are strobed with RAS. Eight column addresses (A0-A8) plus bank select addresses and A10 are strobed with CAS. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A7, BS0, BS1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single...