N2SV12816FS-75B
Overview
The N2SV6H16FS is four-bank Synchronous DRAMs organized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS organized as 2 Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock.
- Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8, Full page Programmable Wrap: Sequential or Interleave Burst Read with Single Write Operation Automatic and Controlled Precharge Command * * * * *
- Dual Data Mask for byte control (x16) Auto Refresh and Self Refresh 64ms refresh period (4K cycle) JEDEC standard 3.3V Power Supply LVTTL compatible Package: 54-pin TSOP (II)
