• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, Full page
• Programmable Wrap: Sequential or Interleave
• Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
64Mb/128Mb Synchronous DRAM
• Dual Data Mask for byte control (x16)
• Auto Refresh and Self Refresh
• 64ms refresh period (4K cycle)
• JEDEC standard 3.3V Power Supply
• LVTTL compatible
• Package: 54-pin TSOP (II)
The N2SV6H16FS is four-bank Synchronous DRAMs orga-
nized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS orga-
nized as 2 Mbit x 16 I/O x 4 Bank. These synchronous
devices achieve high-speed data transfer rates of up to
166MHz by employing a pipeline chip architecture that syn-
chronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eight col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A7, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
The Document is a general product description and is subject to change without notice.