* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE11ED8AJWA Datasheet (285.09 KB)
EBE11ED8AJWA
Elpida Memory
285.09 KB
1gb unbuffered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 1GB Unbuffered DDR2 SDRAM DIMM EBE11ED8AJWA (128M words × 72 bits, 2 Ranks) Specifications Density: 1GB
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