* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE11UD8AHWA Datasheet (250.43 KB)
EBE11UD8AHWA
Elpida Memory
250.43 KB
1gb unbuffered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 1GB Unbuffered DDR2 SDRAM DIMM EBE11UD8AHWA (128M words × 64 bits, 2 Ranks) Specifications Dens.
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