* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column a.

EBE21UE8ABDA

EBE21UE8AADA

EBE21UE8ACFA

EBE21UE8ACSA

EBE21UE8ACUA

EBE21UE8ACWA

EBE21UE8ACWB

EBE21UE8AEFA

EBE21UE8AEFB

EBE21UE8AESA

EBE21UE8AEWA

EBE21UE8AFFA

EBE21UE8AFSA