* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE21UE8ACSA Datasheet (290.85 KB)
EBE21UE8ACSA
Elpida Memory
290.85 KB
2gb ddr2 sdram so-dimm.
DATA SHEET www.DataSheet4U.com 2GB DDR2 SDRAM SO-DIMM EBE21UE8ACSA (256M words × 64 bits, 2 Ranks) Specifications Density: 2GB O.
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