* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE21UE8ACWA Datasheet (280.31 KB)
EBE21UE8ACWA
Elpida Memory
280.31 KB
2gb unbuffered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 2GB Unbuffered DDR2 SDRAM DIMM EBE21UE8ACWA (256M words × 64 bits, 2 Ranks) Specifications Density: 2GB
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