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Elpida Memory

EBE26UC6AASA Datasheet Preview

EBE26UC6AASA Datasheet

256MB DDR2 SDRAM SO-DIMM

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PRELIMINARY DATA SHEET
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256MB DDR2 SDRAM SO-DIMM
EBE26UC6AASA (32M words × 64 bits, 2 Ranks)
Description
The EBE26UC6AASA is 32M words × 64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 8 pieces of 256M bits DDR2
SDRAM sealed in FBGA package. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 4 bits prefetch-pipelined architecture. Data
strobe (DQS and /DQS) both for read and write are
available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay
Locked Loop (DLL) can be set enable or disable. This
module provides high density mounting without utilizing
surface mount technology. Decoupling capacitors are
mounted beside each FBGA on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free
1.8V power supply
Data rate: 533Mbps/400Mbps (max.)
1.8V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(Component)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation.
Document No. E0464E11 (Ver. 1.1) This product became EOL in April, 2005.
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006




Elpida Memory

EBE26UC6AASA Datasheet Preview

EBE26UC6AASA Datasheet

256MB DDR2 SDRAM SO-DIMM

No Preview Available !

Ordering Information
Part number
Data rate
Mbps (max.)
EBE26UC6AASA-5C-E 533
EBE26UC6AASA-4A-E 400
EBE26UC6AASA-4C-E 400
Component
JEDEC speed bin
(CL-tRCD-tRP)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
EBE26UC6AASA
www.DataSheet4U.com
Package
Contact
pad Mounted devices
200-pin SO-DIMM
(lead-free)
Gold
EDE2516AASE-5C
EDE2516AASE-5C, -4A
EDE2516AASE-5C, -4A, -4C
Pin Configurations
1 pin
Front side
39 pin 41 pin
199 pin
2 pin
40 pin 42 pin
Back side
200 pin
Front side
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Pin name
VREF
VSS
DQ0
DQ1
VSS
/DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
/DQS1
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
/DQS2
Pin No.
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Pin name
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
NC
VDD
A12
A9
A8
VDD
A5
A3
Back side
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Pin name
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
/CK0
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
Pin No.
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Pin name
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
/DQS3
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
NC
NC
VDD
A11
A7
A6
VDD
A4
A2
Preliminary Data Sheet E0464E11 (Ver. 1.1)
2


Part Number EBE26UC6AASA
Description 256MB DDR2 SDRAM SO-DIMM
Maker Elpida Memory
Total Page 21 Pages
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