* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE41AF4A1QB Datasheet (273.74 KB)
EBE41AF4A1QB
Elpida Memory
273.74 KB
4gb vlp registered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 4GB VLP Registered DDR2 SDRAM DIMM EBE41AF4A1QB (512M words × 72 bits, 2 Ranks) Specifications .
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