* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE41EF8ABFA Datasheet (286.23 KB)
EBE41EF8ABFA
Elpida Memory
286.23 KB
4gb unbuffered ddr2 sdram dimm.
PRELIMINARY DATA SHEET www.DataSheet4U.com 4GB Unbuffered DDR2 SDRAM DIMM EBE41EF8ABFA (512M words × 72 bits, 2 Ranks) Specifications Dens.
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