* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EBE51RD8AJFA Datasheet (290.12 KB)
EBE51RD8AJFA
Elpida Memory
290.12 KB
512mb registered ddr2 sdram dimm.
DATA SHEET www.DataSheet4U.com 512MB Registered DDR2 SDRAM DIMM EBE51RD8AJFA (64M words × 72 bits, 1 Rank) Specifications Density: 512MB <.
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