EDJ1116DJBG Overview
COVER DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG (128M words × 8 bits) EDJ1116DJBG (64M words × 16 bits) Specifications Density: VDD = 1.5V ± 0.075V Data rate 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max) 1KB page size (EDJ1108DJBG) Row address: A0 to A13 Column address:.
EDJ1116DJBG Key Features
- Double-data-rate architecture: two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better mand and data bus efficiency
- On-Die Termination (ODT) for better signal quality