* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDJ1116DJBG Datasheet (321.34 KB)
EDJ1116DJBG
Elpida Memory
321.34 KB
1g bits ddr3 sdram.
COVER DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG (128M words × 8 bits) EDJ1116DJBG (64M words × 16 bits) Specifications Density: 1G bits
📁 Related Datasheet
EDJ1116DBSE 64M words x 16 bits 1G bits DDR3 SDRAM (Elpida Memory)
EDJ1108DBSE 128M words x 8 bits 1G bits DDR3 SDRAM (Elpida Memory)
EDJ1108DJBG 1G bits DDR3 SDRAM (Elpida Memory)
EDJ2108DEBG 2G bits DDR3 SDRAM (Elpida Memory)
EDJ2116DEBG 2G bits DDR3 SDRAM (Elpida Memory)
EDJ4204EFBG 1024M words x 4 bits 4G bits DDR3L SDRAM (Elpida Memory)
EDJ4208EFBG 512M words x 8 bits 4G bits DDR3L SDRAM (Elpida Memory)
EDJ4208EFBG-L 64 Meg x 8 x 8 banks DDR3L-RS SDRAM (Micron)
EDJ4216EFBG 256M words x 16 bits 4G bits DDR3L SDRAM (Elpida Memory)
EDJ4216EFBG-L 32 Meg x 16 x 8 banks DDR3L-RS SDRAM (Micron)
