EDS6432AFBH Description
The EDS6432AFBH, EDS6432CFBH are 64M bits SDRAMs organized as 524,288 words × 32 bits × 4 banks. All inputs and outputs are synchronized with .. the positive edge of the clock.
EDS6432AFBH Key Features
- 3.3V and 2.5V power supply Clock frequency: 166MHz/133MHz (max.) Single pulsed /RAS ×32 organization 4 banks can operate
- Burst read/write operation and burst read/single write operation capability
- Programmable burst length (BL): 1, 2, 4, 8, full page
- Programmable /CAS latency (CL): 2, 3
- Byte control by DQM
- Refresh cycles: 4096 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh
- FBGA package with lead free solder (Sn-Ag-Cu) RoHS pliant
- 1 Features