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Etron Technology

EM68C08CWAE Datasheet Preview

EM68C08CWAE Datasheet

128M x 8 bit DDRII Synchronous DRAM

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EtronTech
EM68C08CWAE
128M x 8 bit DDRII Synchronous DRAM (SDRAM)
Advance (Rev. 1.3, Oct. /2015)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: VDD & VDDQ = +1.8V ± 0.1V
Operating temperature: TC = 0~85 °C
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 333/400/533 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
8 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5
WRITE latency = READ latency - 1 tCK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
60-ball 8 x 10 x 1.2mm (max) FBGA package
- Pb and Halogen Free
Overview
The EM68C08C is a high-speed CMOS Double-
Data-Rate-Two (DDR2), synchronous dynamic random
- access memory (SDRAM) containing 1024 Mbits in
an 8-bit wide data I/Os. It is internally configured as an
8-bank DRAM, 8 banks x 16Mb addresses x 8 I/Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive latency,
Write latency = Read latency -1, Off-Chip Driver (OCD)
impedance adjustment and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks
(CK rising and CK# falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS#) in
a source synchronous fashion. The address bus is used
to convey row, column, and bank address information
in RAS #, CAS# multiplexing style. Accesses begin
with the registration of a Bank Activate command, and
then it is followed by a Read or Write command. Read
and write accesses to the DDR2 SDRAM are 4 or 8-bit
burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Operating the eight memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
Table 1. Ordering Information
Part Number
Clock Frequency
EM68C08CWAE-18H
533MHz
EM68C08CWAE-25H
400MHz
EM68C08CWAE-3H
333MHz
WA: indicates 8 x 10 x 1.2mm FBGA package
E: indicates Generation Code
H: indicates Pb and Halogen Free
Data Rate
1066Mbps/pin
800Mbps/pin
667Mbps/pin
Power Supply
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
Package
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.




Etron Technology

EM68C08CWAE Datasheet Preview

EM68C08CWAE Datasheet

128M x 8 bit DDRII Synchronous DRAM

No Preview Available !

EtronTech
EM68C08CWAE
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
DDR2-1066
533MHz
DDR2-800
400 MHz
DDR2-667
333 MHz
CAS Latency
7
5
5
tRCD (ns)
13.125
12.5
15
tRP (ns)
13.125
12.5
15
Figure 1. Ball Assignment (FBGA Top View)
123
A VDD
RDQS#
VSS
B DQ6
VSSQ
DM/
RDQS
C VDDQ
DQ1
VDDQ
D DQ4
VSSQ
DQ3
E VDDL
VREF
VSS
F
CKE
WE#
G BA2
BA0
BA1
H A10 A1
J VSS A3
A5
K A7 A9
L VDD A12
NC
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
NC
8
DQS#
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
A13
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
Rev. 1.3
2
Oct. /2015


Part Number EM68C08CWAE
Description 128M x 8 bit DDRII Synchronous DRAM
Maker Etron Technology
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