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EM68916CWQA - 8M x 16 bit DDRII Synchronous DRAM

General Description

Table 3.

Differential Clock: CK, CK# are driven by the system clock.

All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#.

Key Features

  • JEDEC Standard Compliant.
  • JEDEC Standard 1.8V I/O (SSTL_18-compatible).
  • Power supplies: VDD & VDDQ = +1.8V ± 0.1V.
  • Operating temperatue: 0.
  • 85 °C.
  • Supports JEDEC clock jitter specification.
  • Fully synchronous operation.
  • Fast clock rate: 266/333/400MHz.
  • Differential Clock, CK & CK#.
  • Bidirectional single/differential data strobe -DQS & DQS# 4.
  • internal banks for concurrent operation.
  • 4-bit p.

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www.DataSheet.co.kr EtronTech Etron Confidential Features • JEDEC Standard Compliant • JEDEC Standard 1.8V I/O (SSTL_18-compatible) • Power supplies: VDD & VDDQ = +1.8V ± 0.