74F524 Datasheet | Fairchild Semiconductor

74F524 8-Bit Registered parator April 1988 Revised August 1999 74F524 8-Bit Registered parator General Description The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit parator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing “register equal to bus”, “register greater than bus” and “register less than bus” are provided. These...