74F640 Datasheet | Fairchild Semiconductor

Description These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 m A, have 3STATE outputs, and a mon output enable pin. The direction of data flow is determined by the transmit/receive (T/R) input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645. Features s Designed for asynchronous two-way data flow between busses s Outputs sink 64 m A s Transmit/receive (T/R) input controls the direction of data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645 Ordering Code: Order Number 74F640SC 74F640PC 74F645PC Package Number M20B N20A N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram © 1999 Fairchild Semiconductor Corporation DS010267 .fairchildsemi. - 74F645 Unit Loading/Fan Out Pin Names OE T/R A0- A7 B0- B7 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 3.5/0.667 600/106.6 3.5/0.667 600/106.6 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 70 µA/- 0.4 m A - 12 m A/64 m A 70 µA/- 0.4 m A - 12 m A/64 m A Functional Description The output enable (OE) is active LOW. If the device is disabled (OE HIGH), the outputs are in the high impedance state. The transmit/receive input (T/R) controls whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. When T/R is LOW, B data is sent to the A bus. If T/R is HIGH, A data is sent to the B bus. Function Table Inputs OE L L H T/R L H X 74F640 Bus B...