74F647 Datasheet | Philips Semiconductors

FEATURES 74F647/74F649 - High impedance NPN base inputs for reduced loading (20µA in High and Low states) - Independent registers for A and B buses - Multiplexed real-time and stored data - Choice of non-inverting and inverting data paths - Open Collector outputs - 300 mil wide 24-pin Slim Dip package DESCRIPTION The 74F647 and 74F649 Transceivers/Registers consist of bus transceiver circuits with open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a High logic level. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time (transparent mode) data. The DIR determines which bus will receive data when the Output Enable, OE is active Low. In the isolation mode (Output Enable, OE = High), data from Bus A may be stored in the B register and/or data from Bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74F647 and 74F649. TYPICAL fmax 65MHz 65MHz TYPICAL SUPPLY CURRENT (TOTAL) 125m A 125m A TYPE 74F647 74F649 ORDERING INFORMATION DESCRIPTION 24-pin plastic Slim DIP (300mil) 24-pin plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F647N, N74F649N N74F647D, N74F649D PKG DWG # SOT222-1 SOT137-1 PIN CONFIGURATION - 74F647 CPAB 1 SAB 2 DIR 3 24 VCC 23 CPBA 22 SBA 21 OE 20 B0 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 PIN CONFIGURATION - 74F649 CPAB 1 SAB 2 DIR 3 24 VCC...