74FR25900 Datasheet | Fairchild Semiconductor

Description The 74FR25900 is a data bus multiplexer routing any of three 9-bit ports to any other one of the three ports. Readback of data latched from any port onto itself is also possible. The 74FR25900 maintains separate control of all latchenable, output enable and select inputs for maximum flexibility. PINV allows inversion of the data from the C8 to A8 or B8 path. This is useful for control of the parity bit in systems diagnostics. This device includes 25Ω resistors in series with A and B Port outputs. Resistors minimize undershoot and ringing which may damage or corrupt sensitive device inputs driven by these ports. Features s 25Ω series resistors in the port A and B outputs eliminate the need for external resistors when driving MOS inputs such as DRAM arrays s 9-bit data ports for systems carrying parity bits s Readback capability for system self checks. s Independent control lines for maximum flexibility s Guaranteed multiple output switching and 250 p F load delays s Outputs optimized for dynamic bus drive capability s PINV parity control facilitates system diagnostics s 74FR900 option available without output series resistors Ordering Code: Order Number 74FR25900SSC Package Number MS48A Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Description Pin Names LExx OEx PINV S0, S1 A0- A8 B0- B8 C0- C8 Description Latch Enable Inputs Output Enable Inputs Parity Invert Input Select Inputs Port A Inputs or 3-STATE Outputs Port B Inputs or 3-STATE Outputs Port C Inputs or 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS011500 .fairchildsemi. Functional Description The 74FR25900 allows 9-bit data to be transferred from any of three 9-bit I/O ports to either of the two remaining I/O ports. The device employs latches in all paths for either transparent or...