74ALVCF162835 Datasheet | Fairchild Semiconductor

Description The 74ALVCF162835 low voltage 18-bit universal bus driver bines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74ALVCF162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVCF162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVCF162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features I patible with PC133 DIMM module specifications I 1.65V-3.6V VCC specifications provided I 3.6V tolerant outputs I 26Ω series resistors in outputs I t PD (CLK to O n) 3.7 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 7.4 ns max for 1.65V to 1.95V VCC I Power-down high impedance outputs I Latchup conforms to JEDEC JED78 I ESD performance: Human body model > 2000V Machine model >200V Ordering Code: Order Number 74ALVCF162835T Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500668 .fairchildsemi. Connection Diagram Pin Descriptions Pin Names OE LE CLK I1 - I18 O1 - O18 Description Output Enable Input (Active LOW) Latch Enable Input Clock Input Data Inputs 3-STATE Outputs Truth...