74F138 Datasheet | Fairchild Semiconductor

Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using four F138 devices and one inverter. Features s Demultiplexing capability s Multiple input enable for easy expansion s Active LOW mutually exclusive outputs Ordering Code: Order Number 74F138SC 74F138SJ 74F138PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009478 .fairchildsemi. Unit Loading/Fan Out U.L. Pin Names A0- A2 E1, E2 E3 O0- O7 Description HIGH/LOW Address Inputs Enable Inputs (Active LOW) Enable Input (Active HIGH) Outputs (Active LOW) 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A - 1 m A/20 m A Truth Table Inputs E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H Outputs O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Functional Description The F138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active LOW outputs (O0- O7). The F138 features three Enable inputs, two active LOW (E1, E2) and one active HIGH...